1. Field of the Invention
The present invention relates to implementing high-level language code on programmable chips. In one example, the present invention relates to methods and apparatus for providing scheduling optimization for high-level language code.
2. Description of Related Art
Mechanisms for implementing designs of hardware modules from high-level languages such as C or C++ allow designers to work at a relatively high level of abstraction. Designers no longer need to concern themselves as much with low-level circuit implementation details. A variety of tools have been developed to allow implementation of designs such as programmable chip designs from a high-level language such as C or C++.
In one example, code written in a general purpose programming language such as C or C++ is converted into a hardware descriptor language (HDL) file using a tool such as the DK1 Design Suite available from Celoxica Corporation of Abingdon, England. The HDL file can then be synthesized and implemented on a programmable chip such as a programmable logic device (PLD) or a field programmable gate array (FPGA). Some available synthesis tools are Leonardo Spectrum, available from Mentor Graphics Corporation of Wilsonville, Oreg. and Synplify available from Synplicity Corporation of Sunnyvale, Calif.
However, mechanisms for efficiently optimizing code from a high-level language on programmable devices are limited. It is therefore desirable to provide improved methods and apparatus for optimizing implementation of programmable chips.